Citation: Aasen, David, et al. "Roadmap to fault tolerant quantum computation using topological qubit arrays." arXiv preprint arXiv:2502.12252 (2025).
Web: https://arxiv.org/abs/2502.12252
Tags: Hardware, Ising-computer, Majorana-fermions, Universal-scheme
In this paper, Microsoft outlines their roadmap for building a one-million qubit fault-tolerant topological quantum computer. It's a lovely peek into what the future holds. In particular, the authors outline four devices they plan on building - a one tetron device with X and Z logical measurements, a two tetron device with two-qubit measurements, an eight-qubit device with enough two qubit measurements to perform certain Floquet codes, and a much larger device (350ish qubits) which can allow for the implementation of scaling experiments on a code such as the Hastings-Haah code.
The plan is very detailed, and gives a great overview of Microsoft's strategy. The heart of the strategy is the noise models. It is believed by the authors to all the sources of noise are exponentially suppressed with respect to parameters controlled by the experimenter. Additionally, many of the dominant sources of noise are shown to behave as Z-errors, leading to a highly biased noise model. For this reason, the third device (eight qubit device) is going to be designed to run a ladder code, which is well-suited only for highly Z-biased noise.
This article also includes helpful discussion of their readout strategy using quantum dots, and the diagnostics that the authors plan on running to verify that they are implementing the logical operators that the believe they should be. For instance, in the 2-qubit device there is a strategy of gate-set tomography they plan on running to verify that they have approximately created a gate set of one and two qubit measurements.